Commit message (Collapse) | Author | Age | |
---|---|---|---|
* | Added "synth" command | Clifford Wolf | 2014-09-14 |
| | |||
* | Added adff2dff.v (for techmap -share_map) | Clifford Wolf | 2014-08-07 |
| | |||
* | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 |
| | |||
* | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 |
| | |||
* | Merged addition of SED makefile variable from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 |
| | | | | (see https://github.com/cliffordwolf/yosys/pull/28) | ||
* | Added techlibs/common/pmux2mux.v | Clifford Wolf | 2014-01-17 |
| | |||
* | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 |
| | |||
* | Install simlib in datdir | Clifford Wolf | 2013-11-19 |
| | |||
* | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 |