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path: root/techlibs/common/Makefile.inc
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* Added cells.libClifford Wolf2015-01-16
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* Added add_share_file Makefile macroClifford Wolf2015-01-08
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* Fixed build with SMALL=1Clifford Wolf2014-12-30
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* Added "synth" commandClifford Wolf2014-09-14
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* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-07
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-17
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
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* Install simlib in datdirClifford Wolf2013-11-19
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15