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path: root/techlibs/common/simcells.v
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* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
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* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
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* Imported yosys 0.7Ruben Undheim2016-11-03
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* Progress in cell library documentationClifford Wolf2016-02-01
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* Progress on cell help messagesClifford Wolf2015-10-20
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* Progress on cell help messagesClifford Wolf2015-10-17
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* Added more cell descriptionsClifford Wolf2015-10-14
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* Added first help messages for cell typesClifford Wolf2015-10-14
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* Added $tribuf and $_TBUF_ sim modelsClifford Wolf2015-08-16
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* Another block of spelling fixesLarry Doolittle2015-08-14
| | | | Smaller this time
* Fixed trailing whitespacesClifford Wolf2015-07-02
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* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
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* Added $_DFFE_??_ cell typesClifford Wolf2014-12-08
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* Added $_BUF_ cell typeClifford Wolf2014-10-03
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | $_OAI4_
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
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* Added support for dlatchsr cellsClifford Wolf2014-03-31
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24