yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added $equiv cell type	Clifford Wolf	2015-01-19
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*	Progress in memory_bram	Clifford Wolf	2015-01-03
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*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02
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*	New $mem simlib model	Clifford Wolf	2015-01-02
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*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30
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*	Added $dffe cell type	Clifford Wolf	2014-12-08
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*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16
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*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08
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*	Simplified $fa undef model	Clifford Wolf	2014-09-08
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*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08
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*	Added $lcu cell type	Clifford Wolf	2014-09-08
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*	Added "$fa" cell type	Clifford Wolf	2014-09-08
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*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
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*	Added $macc SAT model	Clifford Wolf	2014-09-06
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*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06
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*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
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*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02
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*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02
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*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01
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*	Added $alu cell type	Clifford Wolf	2014-08-30
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*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
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*	RIP $safe_pmux	Clifford Wolf	2014-08-14
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*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
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*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17
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*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16
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*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02
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*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02
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*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
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*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31
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*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29
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*	Added $assert cell	Clifford Wolf	2014-01-19
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*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18
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*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18
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*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18
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*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
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*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15