path: root/techlibs/common/stdcells.v
Commit message (Expand)AuthorAge
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-06
* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-06
* Improved techmap of shift with wide B inputsClifford Wolf2014-03-06
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-18
* Various small cleanups in stdcells.v techmap codeClifford Wolf2013-12-31
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Using simplemap mappers from techmapClifford Wolf2013-11-24
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-07
* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15