| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Added support for non-const === and !== (for miter circuits) | Clifford Wolf | 2013-12-27 |
| * | Using simplemap mappers from techmap | Clifford Wolf | 2013-11-24 |
| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 |
| * | Install simlib in datdir | Clifford Wolf | 2013-11-19 |
| * | Cleanups and bugfixes in response to new internal cell checker | Clifford Wolf | 2013-11-11 |
| * | Fixed techmap of $reduce_xnor with multi-bit outputs | Clifford Wolf | 2013-11-07 |
| * | Fixed techmap of $gt and $ge with multi-bit outputs | Clifford Wolf | 2013-11-06 |
| * | Improved width extension with regard to undef propagation | Clifford Wolf | 2013-11-06 |
| * | Bugfix in dffsr techmap rules | Clifford Wolf | 2013-10-18 |
| * | Added techmap rules for $sr, $dffsr and $dlatch | Clifford Wolf | 2013-10-18 |
| * | Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ | Clifford Wolf | 2013-10-18 |
| * | Added $sr, $dffsr and $dlatch cell types | Clifford Wolf | 2013-10-18 |
| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 |
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index : yosys | |
| Debian dgit repo for package yosys |
| summaryrefslogtreecommitdiff |