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Commit message (Collapse)AuthorAge
* Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-18
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* More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-18
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* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-18
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* Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-18
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* Added $bu0 cell to simlib.vClifford Wolf2014-01-18
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* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-17
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* Various small cleanups in stdcells.v techmap codeClifford Wolf2013-12-31
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* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
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* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
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* Using simplemap mappers from techmapClifford Wolf2013-11-24
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
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* Install simlib in datdirClifford Wolf2013-11-19
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* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
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* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-07
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* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-06
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* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
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* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
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* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
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* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15