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* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-15
* Added $meminit support to "memory" commandClifford Wolf2015-02-14
* Added $meminit cell typeClifford Wolf2015-02-14
* Added "check" commandClifford Wolf2015-02-13
* Some test related fixesClifford Wolf2015-02-12
* Added "make mklibyosys", some minor API changesClifford Wolf2015-02-01
* Added "fsm -encfile"Clifford Wolf2015-01-30
* Added $equiv cell typeClifford Wolf2015-01-19
* Added cells.libClifford Wolf2015-01-16
* Added add_share_file Makefile macroClifford Wolf2015-01-08
* Progress in memory_bramClifford Wolf2015-01-03
* Added proper clkpol support to memory_bramClifford Wolf2015-01-02
* New $mem simlib modelClifford Wolf2015-01-02
* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-30
* Fixed build with SMALL=1Clifford Wolf2014-12-30
* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-24
* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-12
* Added $dffe cell typeClifford Wolf2014-12-08
* Added $_DFFE_??_ cell typesClifford Wolf2014-12-08
* Added "abc" label in synth scriptClifford Wolf2014-10-31
* Added "opt -full" alias for all more aggressive optimizationsClifford Wolf2014-10-31
* Added $_BUF_ cell typeClifford Wolf2014-10-03
* namespace YosysClifford Wolf2014-09-27
* Improvements in "synth" scriptClifford Wolf2014-09-18
* Fixed $macc simlib model for zero-configClifford Wolf2014-09-16
* Added "synth" commandClifford Wolf2014-09-14
* Using alumacc in techmap.vClifford Wolf2014-09-14
* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-08
* Simplified $fa undef modelClifford Wolf2014-09-08
* Fixes and cleanups for blackbox.vClifford Wolf2014-09-08
* Added $lcu cell typeClifford Wolf2014-09-08
* Added "$fa" cell typeClifford Wolf2014-09-08
* Using maccmap for $macc and $mul techmapClifford Wolf2014-09-07
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
* Added $macc SAT modelClifford Wolf2014-09-06
* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-06
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-02
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-01
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added $alu cell typeClifford Wolf2014-08-30
* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-30
* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-18
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-18
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-18
* Multiply using a carry-save accumulatorClifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16