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Author
Age
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namespace Yosys
Clifford Wolf
2014-09-27
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Improvements in "synth" script
Clifford Wolf
2014-09-18
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Fixed $macc simlib model for zero-config
Clifford Wolf
2014-09-16
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Added "synth" command
Clifford Wolf
2014-09-14
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Using alumacc in techmap.v
Clifford Wolf
2014-09-14
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Fixed simlib $macc model for xilinx xsim
Clifford Wolf
2014-09-08
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Simplified $fa undef model
Clifford Wolf
2014-09-08
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Fixes and cleanups for blackbox.v
Clifford Wolf
2014-09-08
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Added $lcu cell type
Clifford Wolf
2014-09-08
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Added "$fa" cell type
Clifford Wolf
2014-09-08
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Using maccmap for $macc and $mul techmap
Clifford Wolf
2014-09-07
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Various bug fixes (related to $macc model testing)
Clifford Wolf
2014-09-06
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Added $macc SAT model
Clifford Wolf
2014-09-06
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Added $macc simlib model (also use as techmap rule for now)
Clifford Wolf
2014-09-06
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Removed $bu0 cell type
Clifford Wolf
2014-09-04
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Undef-related fixes in simlib $alu model
Clifford Wolf
2014-09-02
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Small bug fixes in $not, $neg, and $shiftx models
Clifford Wolf
2014-09-02
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Fixed "test_cell -simlib all"
Clifford Wolf
2014-09-01
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Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
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Added $alu cell type
Clifford Wolf
2014-08-30
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Replaced $__alu CO/CS outputs with full-width CO output
Clifford Wolf
2014-08-30
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Using "via_celltype" in $mul carry-save-acc implementation
Clifford Wolf
2014-08-18
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Performance fix for new $__lcu techmap rule
Clifford Wolf
2014-08-18
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Replaced recursive lcu scheme with bk adder
Clifford Wolf
2014-08-18
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Multiply using a carry-save accumulator
Clifford Wolf
2014-08-16
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵
Clifford Wolf
2014-08-16
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$_OAI4_
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Changes in techmap $__alu interface
Clifford Wolf
2014-08-16
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Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
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Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
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Simplified $__arraymul techmap rule
Clifford Wolf
2014-08-14
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RIP $safe_pmux
Clifford Wolf
2014-08-14
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Added techmap support for actual lookahead carry unit
Clifford Wolf
2014-08-13
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Preparations for lookahead ALU support in techmap.v
Clifford Wolf
2014-08-13
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New interface for $__alu in techmap.v
Clifford Wolf
2014-08-13
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Added adff2dff.v (for techmap -share_map)
Clifford Wolf
2014-08-07
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Implemented recursive techmap
Clifford Wolf
2014-08-03
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Renamed "stdcells.v" to "techmap.v"
Clifford Wolf
2014-07-31
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Reorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf
2014-07-31
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Added techmap CONSTMAP feature
Clifford Wolf
2014-07-30
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New techmap default rules for $shr $sshr $shl $sshl
Clifford Wolf
2014-07-30
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Bugfix in simlib.v for iverilog
Clifford Wolf
2014-07-29
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Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
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Added "make PRETTY=1"
Clifford Wolf
2014-07-24
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Fixed simlib.v model for $mem
Clifford Wolf
2014-07-17
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Updated simlib to new $mem/$memwr interface
Clifford Wolf
2014-07-16
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Added SIMLIB_NOLUT to simlib.v
Clifford Wolf
2014-04-02
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Added SIMLIB_NOSR to simlib.v
Clifford Wolf
2014-04-02
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Added support for dlatchsr cells
Clifford Wolf
2014-03-31
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Merged addition of SED makefile variable from github.com/Siesh1oo/yosys
Clifford Wolf
2014-03-11
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(see https://github.com/cliffordwolf/yosys/pull/28)
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Fixes for improved techmap of shifts with large B inputs
Clifford Wolf
2014-03-06
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