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* Fixed $macc simlib model for zero-configClifford Wolf2014-09-16
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* Added "synth" commandClifford Wolf2014-09-14
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* Using alumacc in techmap.vClifford Wolf2014-09-14
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* Fixed simlib $macc model for xilinx xsimClifford Wolf2014-09-08
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* Simplified $fa undef modelClifford Wolf2014-09-08
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* Fixes and cleanups for blackbox.vClifford Wolf2014-09-08
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* Added $lcu cell typeClifford Wolf2014-09-08
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* Added "$fa" cell typeClifford Wolf2014-09-08
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* Using maccmap for $macc and $mul techmapClifford Wolf2014-09-07
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
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* Added $macc SAT modelClifford Wolf2014-09-06
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* Added $macc simlib model (also use as techmap rule for now)Clifford Wolf2014-09-06
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* Removed $bu0 cell typeClifford Wolf2014-09-04
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* Undef-related fixes in simlib $alu modelClifford Wolf2014-09-02
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* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
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* Fixed "test_cell -simlib all"Clifford Wolf2014-09-01
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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
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* Added $alu cell typeClifford Wolf2014-08-30
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* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-30
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* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-18
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* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-18
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* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-18
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* Multiply using a carry-save accumulatorClifford Wolf2014-08-16
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | $_OAI4_
* Changes in techmap $__alu interfaceClifford Wolf2014-08-16
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* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* Simplified $__arraymul techmap ruleClifford Wolf2014-08-14
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* RIP $safe_pmuxClifford Wolf2014-08-14
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* Added techmap support for actual lookahead carry unitClifford Wolf2014-08-13
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* Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-13
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* New interface for $__alu in techmap.vClifford Wolf2014-08-13
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* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-07
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* Implemented recursive techmapClifford Wolf2014-08-03
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
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* Reorganized stdcells.v (no actual code change, just moved and indented stuff)Clifford Wolf2014-07-31
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* Added techmap CONSTMAP featureClifford Wolf2014-07-30
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* New techmap default rules for $shr $sshr $shl $sshlClifford Wolf2014-07-30
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* Bugfix in simlib.v for iverilogClifford Wolf2014-07-29
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* Fixed simlib.v model for $memClifford Wolf2014-07-17
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* Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-16
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* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-02
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* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-02
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* Added support for dlatchsr cellsClifford Wolf2014-03-31
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* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-06
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* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-06
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* Improved techmap of shift with wide B inputsClifford Wolf2014-03-06
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