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* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Using simplemap mappers from techmapClifford Wolf2013-11-24
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Install simlib in datdirClifford Wolf2013-11-19
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-07
* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15