yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08
*	Progress in memory_bram	Clifford Wolf	2015-01-03
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02
*	New $mem simlib model	Clifford Wolf	2015-01-02
*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30
*	Fixed build with SMALL=1	Clifford Wolf	2014-12-30
*	Improvements in simplemap api, added $ne $nex $eq $eqx support	Clifford Wolf	2014-12-24
*	Removed UTF-8 chars from techmap.v	Clifford Wolf	2014-12-12
*	Added $dffe cell type	Clifford Wolf	2014-12-08
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08
*	Added "abc" label in synth script	Clifford Wolf	2014-10-31
*	Added "opt -full" alias for all more aggressive optimizations	Clifford Wolf	2014-10-31
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Improvements in "synth" script	Clifford Wolf	2014-09-18
*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16
*	Added "synth" command	Clifford Wolf	2014-09-14
*	Using alumacc in techmap.v	Clifford Wolf	2014-09-14
*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08
*	Simplified $fa undef model	Clifford Wolf	2014-09-08
*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08
*	Added $lcu cell type	Clifford Wolf	2014-09-08
*	Added "$fa" cell type	Clifford Wolf	2014-09-08
*	Using maccmap for $macc and $mul techmap	Clifford Wolf	2014-09-07
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
*	Added $macc SAT model	Clifford Wolf	2014-09-06
*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02
*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02
*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
*	Added $alu cell type	Clifford Wolf	2014-08-30
*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30
*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18
*	Performance fix for new $__lcu techmap rule	Clifford Wolf	2014-08-18
*	Replaced recursive lcu scheme with bk adder	Clifford Wolf	2014-08-18
*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16
*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
*	Simplified $__arraymul techmap rule	Clifford Wolf	2014-08-14
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13
*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13
*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13
*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07
*	Implemented recursive techmap	Clifford Wolf	2014-08-03
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31