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* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-01
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added $alu cell typeClifford Wolf2014-08-30
* Replaced $__alu CO/CS outputs with full-width CO outputClifford Wolf2014-08-30
* Using "via_celltype" in $mul carry-save-acc implementationClifford Wolf2014-08-18
* Performance fix for new $__lcu techmap ruleClifford Wolf2014-08-18
* Replaced recursive lcu scheme with bk adderClifford Wolf2014-08-18
* Multiply using a carry-save accumulatorClifford Wolf2014-08-16
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-16
* Changes in techmap $__alu interfaceClifford Wolf2014-08-16
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
* Simplified $__arraymul techmap ruleClifford Wolf2014-08-14
* RIP $safe_pmuxClifford Wolf2014-08-14
* Added techmap support for actual lookahead carry unitClifford Wolf2014-08-13
* Preparations for lookahead ALU support in techmap.vClifford Wolf2014-08-13
* New interface for $__alu in techmap.vClifford Wolf2014-08-13
* Added adff2dff.v (for techmap -share_map)Clifford Wolf2014-08-07
* Implemented recursive techmapClifford Wolf2014-08-03
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
* Reorganized stdcells.v (no actual code change, just moved and indented stuff)Clifford Wolf2014-07-31
* Added techmap CONSTMAP featureClifford Wolf2014-07-30
* New techmap default rules for $shr $sshr $shl $sshlClifford Wolf2014-07-30
* Bugfix in simlib.v for iverilogClifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Fixed simlib.v model for $memClifford Wolf2014-07-17
* Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-16
* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-02
* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-02
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-06
* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-06
* Improved techmap of shift with wide B inputsClifford Wolf2014-03-06
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* More changes to techlibs/common/simlib.v for LECClifford Wolf2014-01-31
* Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)Clifford Wolf2014-01-29
* Added $assert cellClifford Wolf2014-01-19
* Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-18
* More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-18
* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-18
* Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-18
* Added $bu0 cell to simlib.vClifford Wolf2014-01-18
* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-17
* Various small cleanups in stdcells.v techmap codeClifford Wolf2013-12-31
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27