yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30
*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17
*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16
*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02
*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31
*	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11
*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06
*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06
*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31
*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29
*	Added $assert cell	Clifford Wolf	2014-01-19
*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18
*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18
*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18
*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18
*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18
*	Added techlibs/common/pmux2mux.v	Clifford Wolf	2014-01-17
*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24
*	Install simlib in datdir	Clifford Wolf	2013-11-19
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07
*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15