yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
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*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31
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*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29
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*	Added $assert cell	Clifford Wolf	2014-01-19
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*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18
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*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18
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*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18
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*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18
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*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18
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*	Added techlibs/common/pmux2mux.v	Clifford Wolf	2014-01-17
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*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31
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*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
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*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
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*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
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*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24
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*	Install simlib in datdir	Clifford Wolf	2013-11-19
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*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
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*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07
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*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06
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*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
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*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18
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*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18
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*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
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*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
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*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15