index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
techlibs
/
ice40
/
cells_sim.v
Commit message (
Expand
)
Author
Age
*
New upstream version 0.7+20181007git9850de4
Ruben Undheim
2018-10-15
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Work around DDR dout sim glitches in ice40 SB_IO sim model
Clifford Wolf
2016-02-07
*
Merge pull request #108 from cseed/master
Clifford Wolf
2015-12-07
|
\
|
*
Added LO to ICESTORM_LC for LUT cascade route.
Cotton Seed
2015-12-06
*
|
Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling
Clifford Wolf
2015-11-06
*
|
Fixed ice40 handling of negclk RAM40
Clifford Wolf
2015-09-10
|
/
*
Improved handling of "keep" attributes in hierarchical designs in opt_clean
Clifford Wolf
2015-08-12
*
Added iCE40 WARMBOOT cell
Marcus Comstedt
2015-08-06
*
Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)
Clifford Wolf
2015-07-27
*
iCE40 DFF sim models: init Q regs to 0
Clifford Wolf
2015-07-20
*
Avoid tristate warning for blackbox ice40/cells_sim.v
Clifford Wolf
2015-07-18
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Added iCE40 PLL cells
Clifford Wolf
2015-05-31
*
improved ice40 SB_IO sim model
Clifford Wolf
2015-05-23
*
Added ice40 SB_IO sim model
Clifford Wolf
2015-05-23
*
improved iCE40 SB_RAM40_4K simulation model
Clifford Wolf
2015-04-25
*
More iCE40 bram improvements
Clifford Wolf
2015-04-25
*
iCE40 bram tests and fixes
Clifford Wolf
2015-04-24
*
iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models
Clifford Wolf
2015-04-19
*
Changed ice40 ICESTORM_CARRYCONST port name
Clifford Wolf
2015-04-16
*
improved ice40 dff cell mapping
Clifford Wolf
2015-04-16
*
more cells in ice40 cell library
Clifford Wolf
2015-04-14
*
Added very first version of "synth_ice40"
Clifford Wolf
2015-03-05