yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Fixed ice40 handling of negclk RAM40	Clifford Wolf	2015-09-10
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*	Improved handling of "keep" attributes in hierarchical designs in opt_clean	Clifford Wolf	2015-08-12
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*	Added iCE40 WARMBOOT cell	Marcus Comstedt	2015-08-06
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*	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	Clifford Wolf	2015-07-27
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*	iCE40 DFF sim models: init Q regs to 0	Clifford Wolf	2015-07-20
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*	Avoid tristate warning for blackbox ice40/cells_sim.v	Clifford Wolf	2015-07-18
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
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*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31
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*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23
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*	Added ice40 SB_IO sim model	Clifford Wolf	2015-05-23
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*	improved iCE40 SB_RAM40_4K simulation model	Clifford Wolf	2015-04-25
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*	More iCE40 bram improvements	Clifford Wolf	2015-04-25
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*	iCE40 bram tests and fixes	Clifford Wolf	2015-04-24
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*	iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models	Clifford Wolf	2015-04-19
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*	Changed ice40 ICESTORM_CARRYCONST port name	Clifford Wolf	2015-04-16
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*	improved ice40 dff cell mapping	Clifford Wolf	2015-04-16
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*	more cells in ice40 cell library	Clifford Wolf	2015-04-14
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*	Added very first version of "synth_ice40"	Clifford Wolf	2015-03-05