yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	New upstream version 0.7+20180830git0b7a184	Ruben Undheim	2018-08-30
*	Imported yosys 0.7	Ruben Undheim	2016-11-03
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Work around DDR dout sim glitches in ice40 SB_IO sim model	Clifford Wolf	2016-02-07
*	Added dffsr2dff	Clifford Wolf	2016-02-02
*	Re-run ice40_opt in "synth_ice40 -abc2"	Clifford Wolf	2015-12-22
*	Improvements in ice40_opt	Clifford Wolf	2015-12-22
*	Bugfix in ice40_ffinit	Clifford Wolf	2015-12-22
*	Improved ice40_ffinit	Clifford Wolf	2015-12-22
*	Added "synth_ice40 -abc2"	Clifford Wolf	2015-12-08
*	Merge pull request #108 from cseed/master	Clifford Wolf	2015-12-07
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\| *	Added LO to ICESTORM_LC for LUT cascade route.	Cotton Seed	2015-12-06
* \|	Added ice40_ffinit pass	Clifford Wolf	2015-11-26
* \|	Fixed WE/RE usage in iCE40 BRAM mapping	Clifford Wolf	2015-11-24
* \|	Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling	Clifford Wolf	2015-11-06
* \|	Added read-enable to memory model	Clifford Wolf	2015-09-25
* \|	Fixed ice40 handling of negclk RAM40	Clifford Wolf	2015-09-10
* \|	Switched to Python 3	Clifford Wolf	2015-08-22
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*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16
*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16
*	Added tribuf command	Clifford Wolf	2015-08-16
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
*	Improved handling of "keep" attributes in hierarchical designs in opt_clean	Clifford Wolf	2015-08-12
*	Added iCE40 WARMBOOT cell	Marcus Comstedt	2015-08-06
*	Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)	Clifford Wolf	2015-07-27
*	iCE40 DFF sim models: init Q regs to 0	Clifford Wolf	2015-07-20
*	Avoid tristate warning for blackbox ice40/cells_sim.v	Clifford Wolf	2015-07-18
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	iCE40: set min bram efficiency to 2%	Clifford Wolf	2015-06-20
*	synth_ice40 now flattens by default	Clifford Wolf	2015-06-09
*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31
*	Added output args to synth_ice40	Clifford Wolf	2015-05-26
*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23
*	Added ice40 SB_IO sim model	Clifford Wolf	2015-05-23
*	Verific build fixes	Clifford Wolf	2015-05-17
*	ice40_opt bugfix	Clifford Wolf	2015-04-27
*	iCE40: SB_CARRY const fold -> unmap SB_LUT	Clifford Wolf	2015-04-27
*	Added iCE40 const folding support for SB_CARRY	Clifford Wolf	2015-04-27
*	Initialization support for all iCE40 bram modes	Clifford Wolf	2015-04-26
*	initialized iCE40 brams (mode 0)	Clifford Wolf	2015-04-25
*	improved iCE40 SB_RAM40_4K simulation model	Clifford Wolf	2015-04-25
*	More iCE40 bram improvements	Clifford Wolf	2015-04-25
*	iCE40 bram progress	Clifford Wolf	2015-04-24
*	iCE40 bram tests and fixes	Clifford Wolf	2015-04-24
*	Added ice40 bram support	Clifford Wolf	2015-04-24
*	iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models	Clifford Wolf	2015-04-19
*	added sync reset to ice40 test_ffs.sh	Clifford Wolf	2015-04-18
*	Added ice40 test_arith	Clifford Wolf	2015-04-18
*	Added ice40 SB_CARRY support	Clifford Wolf	2015-04-18
*	Added mapping of synchronous set/reset to iCE40 flow	Clifford Wolf	2015-04-17