path: root/techlibs/ice40
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* New upstream version 0.7+20181007git9850de4Ruben Undheim2018-10-15
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-07
* Added dffsr2dffClifford Wolf2016-02-02
* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-22
* Improvements in ice40_optClifford Wolf2015-12-22
* Bugfix in ice40_ffinitClifford Wolf2015-12-22
* Improved ice40_ffinitClifford Wolf2015-12-22
* Added "synth_ice40 -abc2"Clifford Wolf2015-12-08
* Merge pull request #108 from cseed/masterClifford Wolf2015-12-07
| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-06
* | Added ice40_ffinit passClifford Wolf2015-11-26
* | Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-24
* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-06
* | Added read-enable to memory modelClifford Wolf2015-09-25
* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-10
* | Switched to Python 3Clifford Wolf2015-08-22
* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-16
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-16
* Added tribuf commandClifford Wolf2015-08-16
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-12
* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-06
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-27
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-20
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-18
* Fixed trailing whitespacesClifford Wolf2015-07-02
* iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-20
* synth_ice40 now flattens by defaultClifford Wolf2015-06-09
* Added iCE40 PLL cellsClifford Wolf2015-05-31
* Added output args to synth_ice40Clifford Wolf2015-05-26
* improved ice40 SB_IO sim modelClifford Wolf2015-05-23
* Added ice40 SB_IO sim modelClifford Wolf2015-05-23
* Verific build fixesClifford Wolf2015-05-17
* ice40_opt bugfixClifford Wolf2015-04-27
* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-27
* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-27
* Initialization support for all iCE40 bram modesClifford Wolf2015-04-26
* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-25
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-25
* More iCE40 bram improvementsClifford Wolf2015-04-25
* iCE40 bram progressClifford Wolf2015-04-24
* iCE40 bram tests and fixesClifford Wolf2015-04-24
* Added ice40 bram supportClifford Wolf2015-04-24
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-19
* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-18
* Added ice40 test_arithClifford Wolf2015-04-18
* Added ice40 SB_CARRY supportClifford Wolf2015-04-18