Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 |
* | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 |
* | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v | Clifford Wolf | 2013-04-07 |
* | Tiny bugfix in simlib.v | Clifford Wolf | 2013-03-26 |
* | More support code for $sr cells | Clifford Wolf | 2013-03-14 |
* | initial import | Clifford Wolf | 2013-01-05 |