| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 |
| * | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v | Clifford Wolf | 2013-04-07 |
| * | Tiny bugfix in simlib.v | Clifford Wolf | 2013-03-26 |
| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 |
| * | initial import | Clifford Wolf | 2013-01-05 |
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index : yosys | |
| Debian dgit repo for package yosys |
| summaryrefslogtreecommitdiff |