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path: root/techlibs/xilinx/cells_sim.v
Commit message (Expand)AuthorAge
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-04
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-01
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-24
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-16
* added minimalistic xilinx sim modelsClifford Wolf2015-01-08