| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | New upstream version 0.7+20180830git0b7a184 | Ruben Undheim | 2018-08-30 |
| * | Disabled (unused) Xilinx tristate buffers | Clifford Wolf | 2015-02-04 |
| * | Added Xilinx example for Basys3 board | Clifford Wolf | 2015-02-01 |
| * | Fixed xilinx FDSE sim model | Clifford Wolf | 2015-01-24 |
| * | Added MUXCY and XORCY support to synth_xilinx | Clifford Wolf | 2015-01-17 |
| * | Added FF cells to xilinx/cells_sim.v | Clifford Wolf | 2015-01-16 |
| * | added minimalistic xilinx sim models | Clifford Wolf | 2015-01-08 |
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index : yosys | |
| Debian dgit repo for package yosys |
| summaryrefslogtreecommitdiff |