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* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-13
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-01
* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-30
* Added read-enable to memory modelClifford Wolf2015-09-25
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added output args to synth_ice40Clifford Wolf2015-05-26
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added Xilinx bram black-box modulesClifford Wolf2015-04-06
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* no support for 6-series xilinx devicesClifford Wolf2015-02-01
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-01
* Various cleanups in xilinx techlibClifford Wolf2015-01-18
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-17
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-16
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-15
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-13
* Various small improvements to synth_xilinxClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-05
* namespace YosysClifford Wolf2014-09-27
* Added "techmap -share_map" optionClifford Wolf2013-11-24
* Added synth_xilinx commandClifford Wolf2013-10-27