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* New upstream version 0.7+20181007git9850de4Ruben Undheim2018-10-15
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-13
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-01
* Bugfix in Xilinx LUT mappingClifford Wolf2015-10-30
* Added examples/ top-level directoryClifford Wolf2015-10-13
* Added read-enable to memory modelClifford Wolf2015-09-25
* Switched to Python 3Clifford Wolf2015-08-22
* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-16
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-16
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added output args to synth_ice40Clifford Wolf2015-05-26
* Verific build fixesClifford Wolf2015-05-17
* Improved xilinx "bram1" testClifford Wolf2015-04-09
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-09
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-09
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added support for initialized xilinx bramsClifford Wolf2015-04-06
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-06
* Added Xilinx bram black-box modulesClifford Wolf2015-04-06
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-04
* no support for 6-series xilinx devicesClifford Wolf2015-02-01
* Removed old XST-based xilinx examplesClifford Wolf2015-02-01
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-01
* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-01
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-24
* Various cleanups in xilinx techlibClifford Wolf2015-01-18
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-18
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-17
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-16
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-16
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-16
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-16
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-15
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-13
* Added add_share_file Makefile macroClifford Wolf2015-01-08
* added minimalistic xilinx sim modelsClifford Wolf2015-01-08
* More Xilinx bram cleanupsClifford Wolf2015-01-07
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-07
* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* small fix in xilinx/brams.vClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* Various small improvements to synth_xilinxClifford Wolf2015-01-06