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* small fix in xilinx/brams.vClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Various small improvements to synth_xilinxClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-05
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* Towards Xilinx bram supportClifford Wolf2015-01-04
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* Progress in memory_bramClifford Wolf2014-12-31
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* Added memory_bram (not functional yet)Clifford Wolf2014-12-31
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* namespace YosysClifford Wolf2014-09-27
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* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* Added "techmap -share_map" optionClifford Wolf2013-11-24
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* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-24
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* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
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* [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-27
| | | | Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
* Cleanups in xilinx examplesClifford Wolf2013-10-27
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* Added synth_xilinx commandClifford Wolf2013-10-27
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* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-27
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* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
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* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26