yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06
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*	Added Xilinx test case for initialized brams	Clifford Wolf	2015-04-06
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*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06
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*	make all vector-size related integer params in $mem sim model signed	Clifford Wolf	2015-04-05
\| \| \| \| \| \|	this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05
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*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04
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*	Fixes in cmos_cells.v	Clifford Wolf	2015-03-25
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*	Added very first version of "synth_ice40"	Clifford Wolf	2015-03-05
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*	Added $assume cell type	Clifford Wolf	2015-02-26
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*	Added "stat" to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
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*	Added final checks to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
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*	Smaller default parameters in $mem simlib model	Clifford Wolf	2015-02-15
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*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14
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*	Added $meminit cell type	Clifford Wolf	2015-02-14
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*	Added "check" command	Clifford Wolf	2015-02-13
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*	Some test related fixes	Clifford Wolf	2015-02-12
\| \| \| \|	(incl. removal of three bad test cases)
*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04
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*	no support for 6-series xilinx devices	Clifford Wolf	2015-02-01
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*	Removed old XST-based xilinx examples	Clifford Wolf	2015-02-01
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*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01
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*	Added missing ports and parameters to xilinx brams	Clifford Wolf	2015-02-01
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*	Added "make mklibyosys", some minor API changes	Clifford Wolf	2015-02-01
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*	Added "fsm -encfile"	Clifford Wolf	2015-01-30
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*	Fixed xilinx FDSE sim model	Clifford Wolf	2015-01-24
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*	Added $equiv cell type	Clifford Wolf	2015-01-19
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*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18
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*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18
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*	Added synth_xilinx -retime -flatten	Clifford Wolf	2015-01-17
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*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17
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*	Added cells.lib	Clifford Wolf	2015-01-16
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*	Added dff2dffe to synth_xilinx	Clifford Wolf	2015-01-16
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*	Added more FF types to xilinx/cells.v	Clifford Wolf	2015-01-16
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*	Fixed xilinx bram clock inverted config	Clifford Wolf	2015-01-16
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*	Added FF cells to xilinx/cells_sim.v	Clifford Wolf	2015-01-16
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*	Added Xilinx MUXF7 and MUXF8 support	Clifford Wolf	2015-01-15
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*	Various cleanups in synth_xilinx command	Clifford Wolf	2015-01-13
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*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08
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*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08
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*	More Xilinx bram cleanups	Clifford Wolf	2015-01-07
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*	Cleanups in xilinx bram descriptions	Clifford Wolf	2015-01-07
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*	Xilinx RAMB36/RAMB18 memory_bram support complete	Clifford Wolf	2015-01-06
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
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*	small fix in xilinx/brams.v	Clifford Wolf	2015-01-06
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
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*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-05
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*	Towards Xilinx bram support	Clifford Wolf	2015-01-04
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*	Progress in memory_bram	Clifford Wolf	2015-01-03
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