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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Added "make PRETTY=1"Clifford Wolf2014-07-24
* Fixed simlib.v model for $memClifford Wolf2014-07-17
* Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-16
* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-02
* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-02
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Merged addition of SED makefile variable from github.com/Siesh1oo/yosysClifford Wolf2014-03-11
* Fixes for improved techmap of shifts with large B inputsClifford Wolf2014-03-06
* Strictly zero-extend unsigned A-inputs of shift operations in techmapClifford Wolf2014-03-06
* Improved techmap of shift with wide B inputsClifford Wolf2014-03-06
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* More changes to techlibs/common/simlib.v for LECClifford Wolf2014-01-31
* Added test comments to techlibs/cmos/cmos_cells.libClifford Wolf2014-01-29
* Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)Clifford Wolf2014-01-29
* Added $assert cellClifford Wolf2014-01-19
* Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-18
* More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-18
* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-18
* Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-18
* Added $bu0 cell to simlib.vClifford Wolf2014-01-18
* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-17
* Various small cleanups in stdcells.v techmap codeClifford Wolf2013-12-31
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Using simplemap mappers from techmapClifford Wolf2013-11-24
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Added "techmap -share_map" optionClifford Wolf2013-11-24
* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-24
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Updated abcClifford Wolf2013-11-21
* Install simlib in datdirClifford Wolf2013-11-19
* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-18
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-07
* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-31
* [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-27
* Cleanups in xilinx examplesClifford Wolf2013-10-27
* Added synth_xilinx commandClifford Wolf2013-10-27
* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-27
* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26
* Improved xilinx mojo_counter exampleClifford Wolf2013-10-26
* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-26
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18