yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18
*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18
*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18
*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18
*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18
*	Added techlibs/common/pmux2mux.v	Clifford Wolf	2014-01-17
*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
*	Added support for non-const === and !== (for miter circuits)	Clifford Wolf	2013-12-27
*	Using simplemap mappers from techmap	Clifford Wolf	2013-11-24
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24
*	Added "techmap -share_map" option	Clifford Wolf	2013-11-24
*	Fixed xilinx/example_sim_counter test bench	Clifford Wolf	2013-11-24
*	Added more generic _TECHMAP_ wire mechanism to techmap pass	Clifford Wolf	2013-11-23
*	Updated abc	Clifford Wolf	2013-11-21
*	Install simlib in datdir	Clifford Wolf	2013-11-19
*	Added commented-out osu025 maping commands to cmos techmap example	Clifford Wolf	2013-11-18
*	Cleanups and bugfixes in response to new internal cell checker	Clifford Wolf	2013-11-11
*	Fixed techmap of $reduce_xnor with multi-bit outputs	Clifford Wolf	2013-11-07
*	Fixed techmap of $gt and $ge with multi-bit outputs	Clifford Wolf	2013-11-06
*	Improved width extension with regard to undef propagation	Clifford Wolf	2013-11-06
*	Added DFFSR cell to techlibs/cmos/cmos_cells.lib	Clifford Wolf	2013-10-31
*	[EXAMPLES] Ported the mojo counter example to Zynq ZED board.	James Walmsley	2013-10-27
*	Cleanups in xilinx examples	Clifford Wolf	2013-10-27
*	Added synth_xilinx command	Clifford Wolf	2013-10-27
*	Moved simple xilinx counter sim example to subdir	Clifford Wolf	2013-10-27
*	Xilinx mojo_counter example is now working	Clifford Wolf	2013-10-27
*	Renamed techlibs/xilinx7 to techlibs/xilinx	Clifford Wolf	2013-10-26
*	Improved xilinx mojo_counter example	Clifford Wolf	2013-10-26
*	Added another xilinx example (not funcional yet)	Clifford Wolf	2013-10-26
*	Bugfix in dffsr techmap rules	Clifford Wolf	2013-10-18
*	Added techmap rules for $sr, $dffsr and $dlatch	Clifford Wolf	2013-10-18
*	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	Clifford Wolf	2013-10-18
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Added map, par and bitgen to xlinx7 example	Clifford Wolf	2013-10-16
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15
*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14
*	Added spice backend	Clifford Wolf	2013-09-14
*	Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)	Clifford Wolf	2013-08-27
*	Added simple xilinx7 technology mapping files	Clifford Wolf	2013-08-22
*	Implemented same div-by-zero behavior as found in other synthesis tools	Clifford Wolf	2013-08-15
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23
*	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
*	More sign-extension related fixes	Clifford Wolf	2013-06-10
*	Implemented technology mapping for multipliers (using array multiplier)	Clifford Wolf	2013-06-03
*	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	Clifford Wolf	2013-04-07
*	Added EXTRA_TARGETS Makefile variable	Clifford Wolf	2013-03-28
*	Tiny bugfix in simlib.v	Clifford Wolf	2013-03-26