summaryrefslogtreecommitdiff
path: root/techlibs
Commit message (Expand)AuthorAge
* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-18
* Removed cases of trailing comma in stdcells.vClifford Wolf2014-01-18
* Added $bu0 cell to simlib.vClifford Wolf2014-01-18
* Added techlibs/common/pmux2mux.vClifford Wolf2014-01-17
* Various small cleanups in stdcells.v techmap codeClifford Wolf2013-12-31
* Added $bu0 cell (for easy correct $eq/$ne mapping)Clifford Wolf2013-12-28
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Using simplemap mappers from techmapClifford Wolf2013-11-24
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Added "techmap -share_map" optionClifford Wolf2013-11-24
* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-24
* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
* Updated abcClifford Wolf2013-11-21
* Install simlib in datdirClifford Wolf2013-11-19
* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-18
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-07
* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-06
* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
* Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-31
* [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-27
* Cleanups in xilinx examplesClifford Wolf2013-10-27
* Added synth_xilinx commandClifford Wolf2013-10-27
* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-27
* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26
* Improved xilinx mojo_counter exampleClifford Wolf2013-10-26
* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-26
* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-16
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
* Added spice backendClifford Wolf2013-09-14
* Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
* Fixed shift ops with large right hand sideClifford Wolf2013-07-09
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* More sign-extension related fixesClifford Wolf2013-06-10
* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-03
* Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-07
* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-28
* Tiny bugfix in simlib.vClifford Wolf2013-03-26
* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-24
* More support code for $sr cellsClifford Wolf2013-03-14