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* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
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* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
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* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-15
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* Added $meminit support to "memory" commandClifford Wolf2015-02-14
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* Added $meminit cell typeClifford Wolf2015-02-14
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* Added "check" commandClifford Wolf2015-02-13
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* Some test related fixesClifford Wolf2015-02-12
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* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-04
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* no support for 6-series xilinx devicesClifford Wolf2015-02-01
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* Removed old XST-based xilinx examplesClifford Wolf2015-02-01
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* Added Xilinx example for Basys3 boardClifford Wolf2015-02-01
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* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-01
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* Added "make mklibyosys", some minor API changesClifford Wolf2015-02-01
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* Added "fsm -encfile"Clifford Wolf2015-01-30
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* Fixed xilinx FDSE sim modelClifford Wolf2015-01-24
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* Added $equiv cell typeClifford Wolf2015-01-19
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* Various cleanups in xilinx techlibClifford Wolf2015-01-18
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* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-18
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* Added synth_xilinx -retime -flattenClifford Wolf2015-01-17
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* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
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* Added cells.libClifford Wolf2015-01-16
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* Added dff2dffe to synth_xilinxClifford Wolf2015-01-16
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* Added more FF types to xilinx/cells.vClifford Wolf2015-01-16
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* Fixed xilinx bram clock inverted configClifford Wolf2015-01-16
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* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-16
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* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-15
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* Various cleanups in synth_xilinx commandClifford Wolf2015-01-13
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* Added add_share_file Makefile macroClifford Wolf2015-01-08
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* added minimalistic xilinx sim modelsClifford Wolf2015-01-08
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* More Xilinx bram cleanupsClifford Wolf2015-01-07
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* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-07
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* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* small fix in xilinx/brams.vClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Various small improvements to synth_xilinxClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-06
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* Towards Xilinx bram supportClifford Wolf2015-01-05
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* Towards Xilinx bram supportClifford Wolf2015-01-04
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* Progress in memory_bramClifford Wolf2015-01-03
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* Added proper clkpol support to memory_bramClifford Wolf2015-01-02
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* New $mem simlib modelClifford Wolf2015-01-02
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* Progress in memory_bramClifford Wolf2014-12-31
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* Added memory_bram (not functional yet)Clifford Wolf2014-12-31
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* Fixed simlib entries for $memrd and $memwrClifford Wolf2014-12-30
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* Fixed build with SMALL=1Clifford Wolf2014-12-30
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* Improvements in simplemap api, added $ne $nex $eq $eqx supportClifford Wolf2014-12-24
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* Removed UTF-8 chars from techmap.vClifford Wolf2014-12-12
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* Added $dffe cell typeClifford Wolf2014-12-08
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