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* Added iCE40 PLL cellsClifford Wolf2015-05-31
* Added output args to synth_ice40Clifford Wolf2015-05-26
* improved ice40 SB_IO sim modelClifford Wolf2015-05-23
* Added ice40 SB_IO sim modelClifford Wolf2015-05-23
* Verific build fixesClifford Wolf2015-05-17
* ice40_opt bugfixClifford Wolf2015-04-27
* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-27
* Added simplemap $lut supportClifford Wolf2015-04-27
* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-27
* Initialization support for all iCE40 bram modesClifford Wolf2015-04-26
* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-25
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-25
* More iCE40 bram improvementsClifford Wolf2015-04-25
* iCE40 bram progressClifford Wolf2015-04-24
* iCE40 bram tests and fixesClifford Wolf2015-04-24
* Added ice40 bram supportClifford Wolf2015-04-24
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-19
* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-18
* Added ice40 test_arithClifford Wolf2015-04-18
* Added ice40 SB_CARRY supportClifford Wolf2015-04-18
* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-17
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-16
* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-16
* Added simple ice40 dff testsClifford Wolf2015-04-16
* improved ice40 dff cell mappingClifford Wolf2015-04-16
* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-14
* more cells in ice40 cell libraryClifford Wolf2015-04-14
* Improved xilinx "bram1" testClifford Wolf2015-04-09
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-09
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-09
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added support for initialized xilinx bramsClifford Wolf2015-04-06
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-06
* Added Xilinx bram black-box modulesClifford Wolf2015-04-06
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-05
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
* Fixes in cmos_cells.vClifford Wolf2015-03-25
* Added very first version of "synth_ice40"Clifford Wolf2015-03-05
* Added $assume cell typeClifford Wolf2015-02-26
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-15
* Added $meminit support to "memory" commandClifford Wolf2015-02-14
* Added $meminit cell typeClifford Wolf2015-02-14
* Added "check" commandClifford Wolf2015-02-13
* Some test related fixesClifford Wolf2015-02-12
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-04
* no support for 6-series xilinx devicesClifford Wolf2015-02-01
* Removed old XST-based xilinx examplesClifford Wolf2015-02-01