yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
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*	Added iCE40 PLL cells	Clifford Wolf	2015-05-31
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*	Added output args to synth_ice40	Clifford Wolf	2015-05-26
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*	improved ice40 SB_IO sim model	Clifford Wolf	2015-05-23
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*	Added ice40 SB_IO sim model	Clifford Wolf	2015-05-23
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*	Verific build fixes	Clifford Wolf	2015-05-17
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*	ice40_opt bugfix	Clifford Wolf	2015-04-27
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*	iCE40: SB_CARRY const fold -> unmap SB_LUT	Clifford Wolf	2015-04-27
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*	Added simplemap $lut support	Clifford Wolf	2015-04-27
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*	Added iCE40 const folding support for SB_CARRY	Clifford Wolf	2015-04-27
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*	Initialization support for all iCE40 bram modes	Clifford Wolf	2015-04-26
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*	initialized iCE40 brams (mode 0)	Clifford Wolf	2015-04-25
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*	improved iCE40 SB_RAM40_4K simulation model	Clifford Wolf	2015-04-25
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*	More iCE40 bram improvements	Clifford Wolf	2015-04-25
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*	iCE40 bram progress	Clifford Wolf	2015-04-24
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*	iCE40 bram tests and fixes	Clifford Wolf	2015-04-24
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*	Added ice40 bram support	Clifford Wolf	2015-04-24
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*	iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models	Clifford Wolf	2015-04-19
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*	added sync reset to ice40 test_ffs.sh	Clifford Wolf	2015-04-18
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*	Added ice40 test_arith	Clifford Wolf	2015-04-18
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*	Added ice40 SB_CARRY support	Clifford Wolf	2015-04-18
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*	Added mapping of synchronous set/reset to iCE40 flow	Clifford Wolf	2015-04-17
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*	Changed ice40 ICESTORM_CARRYCONST port name	Clifford Wolf	2015-04-16
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*	Fixed "dff2dffe -direct-match"	Clifford Wolf	2015-04-16
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*	Added simple ice40 dff tests	Clifford Wolf	2015-04-16
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*	improved ice40 dff cell mapping	Clifford Wolf	2015-04-16
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*	use "hierarchy -auto-top" in synth_ice40	Clifford Wolf	2015-04-14
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*	more cells in ice40 cell library	Clifford Wolf	2015-04-14
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*	Improved xilinx "bram1" test	Clifford Wolf	2015-04-09
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*	Added memory_bram "make_outreg" feature	Clifford Wolf	2015-04-09
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*	Xilinx DRAMS: RAM64X1D, RAM128X1D	Clifford Wolf	2015-04-09
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*	Towards DRAM support in Xilinx flow	Clifford Wolf	2015-04-09
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*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06
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*	Added Xilinx test case for initialized brams	Clifford Wolf	2015-04-06
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*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06
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*	make all vector-size related integer params in $mem sim model signed	Clifford Wolf	2015-04-05
\| \| \| \| \| \|	this fixes iverilog crashes such as the following: warning: verinum::as_long() truncated 32 bits to 31, returns 2147483647 draw_net_input.c:711: Error: malloc() ran out of memory.
*	Added $_MUX4_, $_MUX8_, and $_MUX16_ cell types	Clifford Wolf	2015-04-05
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*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04
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*	Fixes in cmos_cells.v	Clifford Wolf	2015-03-25
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*	Added very first version of "synth_ice40"	Clifford Wolf	2015-03-05
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*	Added $assume cell type	Clifford Wolf	2015-02-26
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*	Added "stat" to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
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*	Added final checks to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
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*	Smaller default parameters in $mem simlib model	Clifford Wolf	2015-02-15
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*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14
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*	Added $meminit cell type	Clifford Wolf	2015-02-14
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*	Added "check" command	Clifford Wolf	2015-02-13
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*	Some test related fixes	Clifford Wolf	2015-02-12
\| \| \| \|	(incl. removal of three bad test cases)
*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04
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*	no support for 6-series xilinx devices	Clifford Wolf	2015-02-01
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*	Removed old XST-based xilinx examples	Clifford Wolf	2015-02-01
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