yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added $sr, $dffsr and $dlatch cell types	Clifford Wolf	2013-10-18
*	Added map, par and bitgen to xlinx7 example	Clifford Wolf	2013-10-16
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15
*	Added spice testbench to techlibs/cmos	Clifford Wolf	2013-09-14
*	Added spice backend	Clifford Wolf	2013-09-14
*	Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)	Clifford Wolf	2013-08-27
*	Added simple xilinx7 technology mapping files	Clifford Wolf	2013-08-22
*	Implemented same div-by-zero behavior as found in other synthesis tools	Clifford Wolf	2013-08-15
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
*	Added $lut cells and abc lut mapping support	Clifford Wolf	2013-07-23
*	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
*	More fixes for bugs found using xsthammer	Clifford Wolf	2013-06-13
*	More sign-extension related fixes	Clifford Wolf	2013-06-10
*	Implemented technology mapping for multipliers (using array multiplier)	Clifford Wolf	2013-06-03
*	Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v	Clifford Wolf	2013-04-07
*	Added EXTRA_TARGETS Makefile variable	Clifford Wolf	2013-03-28
*	Tiny bugfix in simlib.v	Clifford Wolf	2013-03-26
*	Fixed stdcells.v for $adff with undef reset value	Clifford Wolf	2013-03-24
*	More support code for $sr cells	Clifford Wolf	2013-03-14
*	added .gitignore files	Clifford Wolf	2013-01-05
*	initial import	Clifford Wolf	2013-01-05