path: root/techlibs
Commit message (Expand)AuthorAge
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-16
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
* Added spice backendClifford Wolf2013-09-14
* Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
* Fixed shift ops with large right hand sideClifford Wolf2013-07-09
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* More sign-extension related fixesClifford Wolf2013-06-10
* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-03
* Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-07
* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-28
* Tiny bugfix in simlib.vClifford Wolf2013-03-26
* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-24
* More support code for $sr cellsClifford Wolf2013-03-14
* added .gitignore filesClifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05