summaryrefslogtreecommitdiff
path: root/techlibs
Commit message (Expand)AuthorAge
* Another block of spelling fixesLarry Doolittle2015-08-14
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-12
* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-06
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-27
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-20
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-18
* Improved liberty file test caseClifford Wolf2015-07-06
* Added "synth -nofsm"Clifford Wolf2015-07-02
* Fixed trailing whitespacesClifford Wolf2015-07-02
* iCE40: set min bram efficiency to 2%Clifford Wolf2015-06-20
* Added "synth -nordff -noalumacc"Clifford Wolf2015-06-15
* synth_ice40 now flattens by defaultClifford Wolf2015-06-09
* Added iCE40 PLL cellsClifford Wolf2015-05-31
* Added output args to synth_ice40Clifford Wolf2015-05-26
* improved ice40 SB_IO sim modelClifford Wolf2015-05-23
* Added ice40 SB_IO sim modelClifford Wolf2015-05-23
* Verific build fixesClifford Wolf2015-05-17
* ice40_opt bugfixClifford Wolf2015-04-27
* iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-27
* Added simplemap $lut supportClifford Wolf2015-04-27
* Added iCE40 const folding support for SB_CARRYClifford Wolf2015-04-27
* Initialization support for all iCE40 bram modesClifford Wolf2015-04-26
* initialized iCE40 brams (mode 0)Clifford Wolf2015-04-25
* improved iCE40 SB_RAM40_4K simulation modelClifford Wolf2015-04-25
* More iCE40 bram improvementsClifford Wolf2015-04-25
* iCE40 bram progressClifford Wolf2015-04-24
* iCE40 bram tests and fixesClifford Wolf2015-04-24
* Added ice40 bram supportClifford Wolf2015-04-24
* iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* modelsClifford Wolf2015-04-19
* added sync reset to ice40 test_ffs.shClifford Wolf2015-04-18
* Added ice40 test_arithClifford Wolf2015-04-18
* Added ice40 SB_CARRY supportClifford Wolf2015-04-18
* Added mapping of synchronous set/reset to iCE40 flowClifford Wolf2015-04-17
* Changed ice40 ICESTORM_CARRYCONST port nameClifford Wolf2015-04-16
* Fixed "dff2dffe -direct-match"Clifford Wolf2015-04-16
* Added simple ice40 dff testsClifford Wolf2015-04-16
* improved ice40 dff cell mappingClifford Wolf2015-04-16
* use "hierarchy -auto-top" in synth_ice40Clifford Wolf2015-04-14
* more cells in ice40 cell libraryClifford Wolf2015-04-14
* Improved xilinx "bram1" testClifford Wolf2015-04-09
* Added memory_bram "make_outreg" featureClifford Wolf2015-04-09
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-09
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added support for initialized xilinx bramsClifford Wolf2015-04-06
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-06
* Added Xilinx bram black-box modulesClifford Wolf2015-04-06
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-05
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-19 22:38:03 +0000