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* Added memory_bram "make_outreg" featureClifford Wolf2015-04-09
* Xilinx DRAMS: RAM64X1D, RAM128X1DClifford Wolf2015-04-09
* Towards DRAM support in Xilinx flowClifford Wolf2015-04-09
* Added support for initialized xilinx bramsClifford Wolf2015-04-06
* Added Xilinx test case for initialized bramsClifford Wolf2015-04-06
* Added Xilinx bram black-box modulesClifford Wolf2015-04-06
* make all vector-size related integer params in $mem sim model signedClifford Wolf2015-04-05
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
* Fixes in cmos_cells.vClifford Wolf2015-03-25
* Added very first version of "synth_ice40"Clifford Wolf2015-03-05
* Added $assume cell typeClifford Wolf2015-02-26
* Added "stat" to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Added final checks to "synth" and "synth_xilinx"Clifford Wolf2015-02-15
* Smaller default parameters in $mem simlib modelClifford Wolf2015-02-15
* Added $meminit support to "memory" commandClifford Wolf2015-02-14
* Added $meminit cell typeClifford Wolf2015-02-14
* Added "check" commandClifford Wolf2015-02-13
* Some test related fixesClifford Wolf2015-02-12
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-04
* no support for 6-series xilinx devicesClifford Wolf2015-02-01
* Removed old XST-based xilinx examplesClifford Wolf2015-02-01
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-01
* Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-01
* Added "make mklibyosys", some minor API changesClifford Wolf2015-02-01
* Added "fsm -encfile"Clifford Wolf2015-01-30
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-24
* Added $equiv cell typeClifford Wolf2015-01-19
* Various cleanups in xilinx techlibClifford Wolf2015-01-18
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-18
* Added synth_xilinx -retime -flattenClifford Wolf2015-01-17
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
* Added cells.libClifford Wolf2015-01-16
* Added dff2dffe to synth_xilinxClifford Wolf2015-01-16
* Added more FF types to xilinx/cells.vClifford Wolf2015-01-16
* Fixed xilinx bram clock inverted configClifford Wolf2015-01-16
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-16
* Added Xilinx MUXF7 and MUXF8 supportClifford Wolf2015-01-15
* Various cleanups in synth_xilinx commandClifford Wolf2015-01-13
* Added add_share_file Makefile macroClifford Wolf2015-01-08
* added minimalistic xilinx sim modelsClifford Wolf2015-01-08
* More Xilinx bram cleanupsClifford Wolf2015-01-07
* Cleanups in xilinx bram descriptionsClifford Wolf2015-01-07
* Xilinx RAMB36/RAMB18 memory_bram support completeClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* small fix in xilinx/brams.vClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* Various small improvements to synth_xilinxClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06
* Towards Xilinx bram supportClifford Wolf2015-01-06