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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
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* Added "techmap -share_map" optionClifford Wolf2013-11-24
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* Fixed xilinx/example_sim_counter test benchClifford Wolf2013-11-24
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* Added more generic _TECHMAP_ wire mechanism to techmap passClifford Wolf2013-11-23
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* Updated abcClifford Wolf2013-11-21
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* Install simlib in datdirClifford Wolf2013-11-19
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* Added commented-out osu025 maping commands to cmos techmap exampleClifford Wolf2013-11-18
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* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
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* Fixed techmap of $reduce_xnor with multi-bit outputsClifford Wolf2013-11-07
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* Fixed techmap of $gt and $ge with multi-bit outputsClifford Wolf2013-11-06
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* Improved width extension with regard to undef propagationClifford Wolf2013-11-06
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* Added DFFSR cell to techlibs/cmos/cmos_cells.libClifford Wolf2013-10-31
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* [EXAMPLES] Ported the mojo counter example to Zynq ZED board.James Walmsley2013-10-27
| | | | Will be adding a tutorial on this to verilog.james.walms.co.uk in a few days.
* Cleanups in xilinx examplesClifford Wolf2013-10-27
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* Added synth_xilinx commandClifford Wolf2013-10-27
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* Moved simple xilinx counter sim example to subdirClifford Wolf2013-10-27
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* Xilinx mojo_counter example is now workingClifford Wolf2013-10-27
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* Renamed techlibs/xilinx7 to techlibs/xilinxClifford Wolf2013-10-26
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* Improved xilinx mojo_counter exampleClifford Wolf2013-10-26
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* Added another xilinx example (not funcional yet)Clifford Wolf2013-10-26
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* Bugfix in dffsr techmap rulesClifford Wolf2013-10-18
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* Added techmap rules for $sr, $dffsr and $dlatchClifford Wolf2013-10-18
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* Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_Clifford Wolf2013-10-18
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* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
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* Added map, par and bitgen to xlinx7 exampleClifford Wolf2013-10-16
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
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* Added spice testbench to techlibs/cmosClifford Wolf2013-09-14
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* Added spice backendClifford Wolf2013-09-14
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* Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)Clifford Wolf2013-08-27
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* Added simple xilinx7 technology mapping filesClifford Wolf2013-08-22
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* Implemented same div-by-zero behavior as found in other synthesis toolsClifford Wolf2013-08-15
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* Added $div and $mod technology mappingClifford Wolf2013-08-09
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* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23
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* Fixed shift ops with large right hand sideClifford Wolf2013-07-09
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* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
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* More sign-extension related fixesClifford Wolf2013-06-10
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* Implemented technology mapping for multipliers (using array multiplier)Clifford Wolf2013-06-03
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* Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-07
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* Added EXTRA_TARGETS Makefile variableClifford Wolf2013-03-28
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* Tiny bugfix in simlib.vClifford Wolf2013-03-26
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* Fixed stdcells.v for $adff with undef reset valueClifford Wolf2013-03-24
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* More support code for $sr cellsClifford Wolf2013-03-14
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* added .gitignore filesClifford Wolf2013-01-05
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* initial importClifford Wolf2013-01-05