Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Added $lut cells and abc lut mapping support | Clifford Wolf | 2013-07-23 |
* | Fixed shift ops with large right hand side | Clifford Wolf | 2013-07-09 |
* | More fixes for bugs found using xsthammer | Clifford Wolf | 2013-06-13 |
* | More sign-extension related fixes | Clifford Wolf | 2013-06-10 |
* | Implemented technology mapping for multipliers (using array multiplier) | Clifford Wolf | 2013-06-03 |
* | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v | Clifford Wolf | 2013-04-07 |
* | Added EXTRA_TARGETS Makefile variable | Clifford Wolf | 2013-03-28 |
* | Tiny bugfix in simlib.v | Clifford Wolf | 2013-03-26 |
* | Fixed stdcells.v for $adff with undef reset value | Clifford Wolf | 2013-03-24 |
* | More support code for $sr cells | Clifford Wolf | 2013-03-14 |
* | added .gitignore files | Clifford Wolf | 2013-01-05 |
* | initial import | Clifford Wolf | 2013-01-05 |