yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added cells.lib	Clifford Wolf	2015-01-16
*	Added dff2dffe to synth_xilinx	Clifford Wolf	2015-01-16
*	Added more FF types to xilinx/cells.v	Clifford Wolf	2015-01-16
*	Fixed xilinx bram clock inverted config	Clifford Wolf	2015-01-16
*	Added FF cells to xilinx/cells_sim.v	Clifford Wolf	2015-01-16
*	Added Xilinx MUXF7 and MUXF8 support	Clifford Wolf	2015-01-15
*	Various cleanups in synth_xilinx command	Clifford Wolf	2015-01-13
*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08
*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08
*	More Xilinx bram cleanups	Clifford Wolf	2015-01-07
*	Cleanups in xilinx bram descriptions	Clifford Wolf	2015-01-07
*	Xilinx RAMB36/RAMB18 memory_bram support complete	Clifford Wolf	2015-01-06
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
*	small fix in xilinx/brams.v	Clifford Wolf	2015-01-06
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05
*	Towards Xilinx bram support	Clifford Wolf	2015-01-04
*	Progress in memory_bram	Clifford Wolf	2015-01-03
*	Added proper clkpol support to memory_bram	Clifford Wolf	2015-01-02
*	New $mem simlib model	Clifford Wolf	2015-01-02
*	Progress in memory_bram	Clifford Wolf	2014-12-31
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31
*	Fixed simlib entries for $memrd and $memwr	Clifford Wolf	2014-12-30
*	Fixed build with SMALL=1	Clifford Wolf	2014-12-30
*	Improvements in simplemap api, added $ne $nex $eq $eqx support	Clifford Wolf	2014-12-24
*	Removed UTF-8 chars from techmap.v	Clifford Wolf	2014-12-12
*	Added $dffe cell type	Clifford Wolf	2014-12-08
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08
*	Added "abc" label in synth script	Clifford Wolf	2014-10-31
*	Added "opt -full" alias for all more aggressive optimizations	Clifford Wolf	2014-10-31
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Improvements in "synth" script	Clifford Wolf	2014-09-18
*	Fixed $macc simlib model for zero-config	Clifford Wolf	2014-09-16
*	Added "synth" command	Clifford Wolf	2014-09-14
*	Using alumacc in techmap.v	Clifford Wolf	2014-09-14
*	Fixed simlib $macc model for xilinx xsim	Clifford Wolf	2014-09-08
*	Simplified $fa undef model	Clifford Wolf	2014-09-08
*	Fixes and cleanups for blackbox.v	Clifford Wolf	2014-09-08
*	Added $lcu cell type	Clifford Wolf	2014-09-08
*	Added "$fa" cell type	Clifford Wolf	2014-09-08
*	Using maccmap for $macc and $mul techmap	Clifford Wolf	2014-09-07
*	Various bug fixes (related to $macc model testing)	Clifford Wolf	2014-09-06
*	Added $macc SAT model	Clifford Wolf	2014-09-06
*	Added $macc simlib model (also use as techmap rule for now)	Clifford Wolf	2014-09-06
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04
*	Undef-related fixes in simlib $alu model	Clifford Wolf	2014-09-02