yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Small bug fixes in $not, $neg, and $shiftx models	Clifford Wolf	2014-09-02
\|
*	Fixed "test_cell -simlib all"	Clifford Wolf	2014-09-01
\|
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31
\|
*	Added $alu cell type	Clifford Wolf	2014-08-30
\|
*	Replaced $__alu CO/CS outputs with full-width CO output	Clifford Wolf	2014-08-30
\|
*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18
\|
*	Performance fix for new $__lcu techmap rule	Clifford Wolf	2014-08-18
\|
*	Replaced recursive lcu scheme with bk adder	Clifford Wolf	2014-08-18
\|
*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16
\|
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16
\| \| \| \|	$_OAI4_
*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16
\|
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
\|
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
\|
*	Simplified $__arraymul techmap rule	Clifford Wolf	2014-08-14
\|
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
\|
*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13
\|
*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13
\|
*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13
\|
*	Added adff2dff.v (for techmap -share_map)	Clifford Wolf	2014-08-07
\|
*	Implemented recursive techmap	Clifford Wolf	2014-08-03
\|
*	Renamed "stdcells.v" to "techmap.v"	Clifford Wolf	2014-07-31
\|
*	Reorganized stdcells.v (no actual code change, just moved and indented stuff)	Clifford Wolf	2014-07-31
\|
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30
\|
*	New techmap default rules for $shr $sshr $shl $sshl	Clifford Wolf	2014-07-30
\|
*	Bugfix in simlib.v for iverilog	Clifford Wolf	2014-07-29
\|
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29
\|
*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24
\|
*	Fixed simlib.v model for $mem	Clifford Wolf	2014-07-17
\|
*	Updated simlib to new $mem/$memwr interface	Clifford Wolf	2014-07-16
\|
*	Added SIMLIB_NOLUT to simlib.v	Clifford Wolf	2014-04-02
\|
*	Added SIMLIB_NOSR to simlib.v	Clifford Wolf	2014-04-02
\|
*	Added support for dlatchsr cells	Clifford Wolf	2014-03-31
\|
*	Merged addition of SED makefile variable from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Fixes for improved techmap of shifts with large B inputs	Clifford Wolf	2014-03-06
\|
*	Strictly zero-extend unsigned A-inputs of shift operations in techmap	Clifford Wolf	2014-03-06
\|
*	Improved techmap of shift with wide B inputs	Clifford Wolf	2014-03-06
\|
*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07
\|
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
\|
*	More changes to techlibs/common/simlib.v for LEC	Clifford Wolf	2014-01-31
\|
*	Added test comments to techlibs/cmos/cmos_cells.lib	Clifford Wolf	2014-01-29
\|
*	Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)	Clifford Wolf	2014-01-29
\|
*	Added $assert cell	Clifford Wolf	2014-01-19
\|
*	Fixed $lut simlib model for a wider range of tools	Clifford Wolf	2014-01-18
\|
*	More changes to simlib to make it friendlier to a wider range of tools	Clifford Wolf	2014-01-18
\|
*	Fixed a type in $mem model in simlib.v	Clifford Wolf	2014-01-18
\|
*	Removed cases of trailing comma in stdcells.v	Clifford Wolf	2014-01-18
\|
*	Added $bu0 cell to simlib.v	Clifford Wolf	2014-01-18
\|
*	Added techlibs/common/pmux2mux.v	Clifford Wolf	2014-01-17
\|
*	Various small cleanups in stdcells.v techmap code	Clifford Wolf	2013-12-31
\|
*	Added $bu0 cell (for easy correct $eq/$ne mapping)	Clifford Wolf	2013-12-28
\|