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* New upstream version 0.8Ruben Undheim2018-10-17
* New upstream version 0.7+20181007git9850de4Ruben Undheim2018-10-15
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Imported yosys 0.7Ruben Undheim2016-11-03
* Squashed commit of the following:Ruben Undheim2016-09-23
* Run dffsr2dff in synth_xilinxClifford Wolf2016-02-13
* Work around DDR dout sim glitches in ice40 SB_IO sim modelClifford Wolf2016-02-07
* Added dffsr2dffClifford Wolf2016-02-02
* Progress in cell library documentationClifford Wolf2016-02-01
* Added "abc -luts" option, Improved Xilinx logic mappingClifford Wolf2016-02-01
* Re-run ice40_opt in "synth_ice40 -abc2"Clifford Wolf2015-12-22
* Improvements in ice40_optClifford Wolf2015-12-22
* Bugfix in ice40_ffinitClifford Wolf2015-12-22
* Improved ice40_ffinitClifford Wolf2015-12-22
* Run opt_const before check in default scriptsClifford Wolf2015-12-22
* Added "synth_ice40 -abc2"Clifford Wolf2015-12-08
* Merge pull request #108 from cseed/masterClifford Wolf2015-12-07
| * Added LO to ICESTORM_LC for LUT cascade route.Cotton Seed2015-12-06
* | Added ice40_ffinit passClifford Wolf2015-11-26
* | Fixed WE/RE usage in iCE40 BRAM mappingClifford Wolf2015-11-24
* | Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handlingClifford Wolf2015-11-06
* | Bugfix in Xilinx LUT mappingClifford Wolf2015-10-30
* | Progress on cell help messagesClifford Wolf2015-10-20
* | Progress on cell help messagesClifford Wolf2015-10-17
* | Added "prep" commandClifford Wolf2015-10-14
* | Added more cell descriptionsClifford Wolf2015-10-14
* | Added first help messages for cell typesClifford Wolf2015-10-14
* | Added examples/ top-level directoryClifford Wolf2015-10-13
* | Added read-enable to memory modelClifford Wolf2015-09-25
* | Added nlutmapClifford Wolf2015-09-18
* | Renamed GreenPAK4 cells, improved GP4 DFF mappingClifford Wolf2015-09-18
* | Fixed copy&paste typo in synth_greenpak4Clifford Wolf2015-09-16
* | Added GreenPAK4 skeletonClifford Wolf2015-09-16
* | Fixed ice40 handling of negclk RAM40Clifford Wolf2015-09-10
* | Switched to Python 3Clifford Wolf2015-08-22
* Another bugfix for ice40 and xilinx brams_init make rulesClifford Wolf2015-08-16
* Fixed Makefile rules for generated share filesClifford Wolf2015-08-16
* Added $tribuf and $_TBUF_ sim modelsClifford Wolf2015-08-16
* Added tribuf commandClifford Wolf2015-08-16
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-16
* Another block of spelling fixesLarry Doolittle2015-08-14
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
* Improved handling of "keep" attributes in hierarchical designs in opt_cleanClifford Wolf2015-08-12
* Added iCE40 WARMBOOT cellMarcus Comstedt2015-08-06
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)Clifford Wolf2015-07-27
* iCE40 DFF sim models: init Q regs to 0Clifford Wolf2015-07-20
* Avoid tristate warning for blackbox ice40/cells_sim.vClifford Wolf2015-07-18
* Improved liberty file test caseClifford Wolf2015-07-06
* Added "synth -nofsm"Clifford Wolf2015-07-02