| Commit message (Collapse) | Author | Age | |
|---|---|---|---|
| * | Added yet another resource sharing test case | Clifford Wolf | 2014-07-20 |
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| * | now ignore init attributes on non-register wires in sat command | Clifford Wolf | 2014-07-05 |
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| * | Added read_verilog -sv options, added support for bit, logic, | Clifford Wolf | 2014-06-12 |
| | | | | | allways_ff, always_comb, and always_latch | ||
| * | Added test cases for expose -evert-dff | Clifford Wolf | 2014-02-08 |
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| * | Added splice command | Clifford Wolf | 2014-02-07 |
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| * | Added counters sat test case | Clifford Wolf | 2014-02-06 |
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| * | Added test cases for sat command | Clifford Wolf | 2014-02-04 |
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index : yosys | |
| Debian dgit repo for package yosys |
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