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* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
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* Added yet another resource sharing test caseClifford Wolf2014-07-20
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* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-05
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
| | | | allways_ff, always_comb, and always_latch
* Added test cases for expose -evert-dffClifford Wolf2014-02-08
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* Added splice commandClifford Wolf2014-02-07
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* Added counters sat test caseClifford Wolf2014-02-06
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* Added test cases for sat commandClifford Wolf2014-02-04