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* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-12
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-05
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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-05
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* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-30
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* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-28
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* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-25
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* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-17
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* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-17
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* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-17
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* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
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* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-02
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* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-25
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* Little steps in realmath test benchClifford Wolf2014-06-21
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* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-17
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* Removed long running tests from tests/simple/realexpr.v (replaced by ↵Clifford Wolf2014-06-15
| | | | tests/realmath)
* Added tests/realmath to "make test"Clifford Wolf2014-06-15
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* Added support for math functionsClifford Wolf2014-06-14
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* Added realexpr.v test caseClifford Wolf2014-06-14
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* added tests for new verilog featuresClifford Wolf2014-06-07
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* Added tests/simple/repwhile.vClifford Wolf2014-06-06
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* Progress in Verific bindingsClifford Wolf2014-03-17
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
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* Bugfix in name resolution with generate blocksClifford Wolf2014-01-30
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* Added correct handling of $memwr priorityClifford Wolf2014-01-03
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* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
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* Added multiplier test case from eda playgroundClifford Wolf2013-12-18
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* Added elsif preproc supportClifford Wolf2013-12-18
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* Added support for macro argumentsClifford Wolf2013-12-18
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* Various improvements in support for generate statementsClifford Wolf2013-12-04
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* Replaced RTLIL::Const::str with generic decoder methodClifford Wolf2013-12-04
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* Fix in sincos testbench genClifford Wolf2013-12-04
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* Added sincos test caseClifford Wolf2013-12-04
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* Implemented correct handling of signed module parametersClifford Wolf2013-11-24
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* Added modelsim support to autotestClifford Wolf2013-11-24
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* Another name resolution bugfix for generate blocksClifford Wolf2013-11-20
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* Implemented indexed part selectsClifford Wolf2013-11-20
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* Implemented part/bit select on memory readClifford Wolf2013-11-20
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* Added additional mem2reg testcaseClifford Wolf2013-11-18
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* Fixed parsing of default cases when not last caseClifford Wolf2013-11-18
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* Fixed handling of power operatorClifford Wolf2013-11-07
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* Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing ↵Clifford Wolf2013-11-02
| | | | before constfold fixes)
* Various ast changes for early expression width detection (prep for constfold ↵Clifford Wolf2013-11-02
| | | | fixes)
* Added support for complex set-reset flip-flops in proc_dffClifford Wolf2013-10-24
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* Improved handling of dff with async resetsClifford Wolf2013-10-21
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* Added support for "2**n" shifter encodingClifford Wolf2013-08-12
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* Added $div and $mod technology mappingClifford Wolf2013-08-09
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* More fixes in ternary op sign handlingClifford Wolf2013-07-12
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* Fixed sign handling in ternary operatorClifford Wolf2013-07-12
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* Another vloghammer related bugfixClifford Wolf2013-07-11
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* More fixes in ast expression sign/width handlingClifford Wolf2013-07-09
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