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* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* Fixed a bug in AST frontend for cases with non-blocking assigned variables as...Clifford Wolf2013-04-13
* Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-31
* Renamed hansimem.v test case to mem_arst.vClifford Wolf2013-03-24
* Added hansimem testcase (memory with async reset)Clifford Wolf2013-03-24
* added ckeck for Icarus Verilog, otherwise the tests are silently stoppedJohann Glaser2013-03-17
* added more .gitignore files (make test)Clifford Wolf2013-01-05
* initial importClifford Wolf2013-01-05