yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Added tests/realmath to "make test"	Clifford Wolf	2014-06-15
*	Added support for math functions	Clifford Wolf	2014-06-14
*	Added realexpr.v test case	Clifford Wolf	2014-06-14
*	added tests for new verilog features	Clifford Wolf	2014-06-07
*	Added tests/simple/repwhile.v	Clifford Wolf	2014-06-06
*	Progress in Verific bindings	Clifford Wolf	2014-03-17
*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03
*	Bugfix in name resolution with generate blocks	Clifford Wolf	2014-01-30
*	Added correct handling of $memwr priority	Clifford Wolf	2014-01-03
*	Added proper === and !== support in constant expressions	Clifford Wolf	2013-12-27
*	Added multiplier test case from eda playground	Clifford Wolf	2013-12-18
*	Added elsif preproc support	Clifford Wolf	2013-12-18
*	Added support for macro arguments	Clifford Wolf	2013-12-18
*	Various improvements in support for generate statements	Clifford Wolf	2013-12-04
*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04
*	Fix in sincos testbench gen	Clifford Wolf	2013-12-04
*	Added sincos test case	Clifford Wolf	2013-12-04
*	Implemented correct handling of signed module parameters	Clifford Wolf	2013-11-24
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24
*	Another name resolution bugfix for generate blocks	Clifford Wolf	2013-11-20
*	Implemented indexed part selects	Clifford Wolf	2013-11-20
*	Implemented part/bit select on memory read	Clifford Wolf	2013-11-20
*	Added additional mem2reg testcase	Clifford Wolf	2013-11-18
*	Fixed parsing of default cases when not last case	Clifford Wolf	2013-11-18
*	Fixed handling of power operator	Clifford Wolf	2013-11-07
*	Behavior should be identical now to rev. 0b4a64ac6adbd6 (next: testing before...	Clifford Wolf	2013-11-02
*	Various ast changes for early expression width detection (prep for constfold ...	Clifford Wolf	2013-11-02
*	Added support for complex set-reset flip-flops in proc_dff	Clifford Wolf	2013-10-24
*	Improved handling of dff with async resets	Clifford Wolf	2013-10-21
*	Added support for "2**n" shifter encoding	Clifford Wolf	2013-08-12
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09
*	More fixes in ternary op sign handling	Clifford Wolf	2013-07-12
*	Fixed sign handling in ternary operator	Clifford Wolf	2013-07-12
*	Another vloghammer related bugfix	Clifford Wolf	2013-07-11
*	More fixes in ast expression sign/width handling	Clifford Wolf	2013-07-09
*	Merge branch 'master' of github.com:cliffordwolf/yosys	Clifford Wolf	2013-07-09
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\| *	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09
* \|	Fixed shift ops with large right hand side	Clifford Wolf	2013-07-09
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04
*	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13
*	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31
*	Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	2013-03-24
*	Added hansimem testcase (memory with async reset)	Clifford Wolf	2013-03-24
*	added ckeck for Icarus Verilog, otherwise the tests are silently stopped	Johann Glaser	2013-03-17
*	added more .gitignore files (make test)	Clifford Wolf	2013-01-05
*	initial import	Clifford Wolf	2013-01-05