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Author
Age
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Added $div and $mod technology mapping
Clifford Wolf
2013-08-09
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More fixes in ternary op sign handling
Clifford Wolf
2013-07-12
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Fixed sign handling in ternary operator
Clifford Wolf
2013-07-12
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Another vloghammer related bugfix
Clifford Wolf
2013-07-11
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More fixes in ast expression sign/width handling
Clifford Wolf
2013-07-09
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Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2013-07-09
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Major redesign of expr width/sign detecion (verilog/ast frontend)
Clifford Wolf
2013-07-09
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Fixed shift ops with large right hand side
Clifford Wolf
2013-07-09
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Fixed another bug found using vloghammer
Clifford Wolf
2013-07-07
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Added defparam support to Verilog/AST frontend
Clifford Wolf
2013-07-04
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Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵
Clifford Wolf
2013-04-13
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as case values
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Added test cases from 2012 paper on comparison of foss verilog synthesis tools
Clifford Wolf
2013-03-31
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Renamed hansimem.v test case to mem_arst.v
Clifford Wolf
2013-03-24
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Added hansimem testcase (memory with async reset)
Clifford Wolf
2013-03-24
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added ckeck for Icarus Verilog, otherwise the tests are silently stopped
Johann Glaser
2013-03-17
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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added more .gitignore files (make test)
Clifford Wolf
2013-01-05
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initial import
Clifford Wolf
2013-01-05
