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path: root/tests/tools/autotest.sh
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* Set path to berkeley-abc instead of relative path to yosys-abcRuben Undheim2019-10-18
* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Squashed commit of the following:Ruben Undheim2016-09-23
* Another block of spelling fixesLarry Doolittle2015-08-14
* Some test related fixesClifford Wolf2015-02-12
* Added "synth" commandClifford Wolf2014-09-14
* Fixed autotest for non-basename argumentsClifford Wolf2014-09-06
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-30
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-03
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-01
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-30
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-29
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-21
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-17
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-16
* Progress in Verific bindingsClifford Wolf2014-03-17
* Progress in Verific bindingsClifford Wolf2014-03-14
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-15
* Updated ABC and some related changesClifford Wolf2014-02-13
* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-12
* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-03
* Added autotest.sh -p optionClifford Wolf2014-01-02
* Use "abc -dff" in "make test"Clifford Wolf2013-12-31
* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-31
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Added modelsim support to autotestClifford Wolf2013-11-24
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
* Added $div and $mod technology mappingClifford Wolf2013-08-09
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* initial importClifford Wolf2013-01-05