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* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-19
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* Added frontend (-f) option to autotest.shClifford Wolf2014-02-15
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* Updated ABC and some related changesClifford Wolf2014-02-13
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* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-12
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* Removed old unused files from tests/Clifford Wolf2014-02-05
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* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-03
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* Added autotest.sh -p optionClifford Wolf2014-01-02
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* Use "abc -dff" in "make test"Clifford Wolf2013-12-31
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* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-31
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
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* Added modelsim support to autotestClifford Wolf2013-11-24
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
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* Added $div and $mod technology mappingClifford Wolf2013-08-09
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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
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* Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-14
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* Some improvements in vcdcd.plClifford Wolf2013-05-14
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* added more .gitignore files (make test)Clifford Wolf2013-01-05
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* initial importClifford Wolf2013-01-05