| Commit message (Expand) | Author | Age | |
|---|---|---|---|
| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 |
| * | Added modelsim support to autotest | Clifford Wolf | 2013-11-24 |
| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 |
| * | Added $div and $mod technology mapping | Clifford Wolf | 2013-08-09 |
| * | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 |
| * | Improved vcdcd.pl (added -d option) | Clifford Wolf | 2013-05-14 |
| * | Some improvements in vcdcd.pl | Clifford Wolf | 2013-05-14 |
| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 |
| * | initial import | Clifford Wolf | 2013-01-05 |
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index : yosys | |
| Debian dgit repo for package yosys |
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